1. Field of the Invention
The present invention relates to a display device, and more particularly to a display device which includes a drive circuit having a CMOS shift register circuit which is constituted of a CMOS circuit.
2. Description of the Related Art
In general, in an active matrix liquid crystal display device which uses thin film transistors (TFT: Thin Film Transistor) as active elements, a scanning circuit is used for sequentially applying a selective scanning voltage to scanning lines.
FIG. 13 is a block diagram showing the circuit constitution of a conventional scanning circuit. In the drawing, numeral 10 indicates a shift register circuit and numeral 11 indicates a level shift circuit.
As the shift register circuit 10 shown in FIG. 13, there has been known a CMOS shift register circuit which is constituted of a CMOS (Complementary Metal Oxide Semiconductor) circuit or an nMOS single-channel shift register circuit which is constituted of nMOS single-channel transistor.
FIG. 14 is a circuit diagram showing a unit circuit of the conventional CMOS shift register circuit which adopts the circuit constitution described in JP-A-2000-227784 or JP-A-10-199284.
The unit circuit shown in FIG. 14 includes a clocked inverter (INV1) which inverts an input signal (IN), an inverter (INV2) which re-inverts an inverted signal of the input signal (IN), and a clocked inverter (INV3) which feedbacks are inverted signal of the input signal (IN) to an input of the inverter (INV2).
Then, an output of the inverter (INV2) becomes a transfer output (TRN). Further, the input signal (IN) and the transfer output (TRN) are inputted to a NAND circuit (NAND). An output signal of the NAND circuit (NAND) is inverted by an inverter (INV4) thus generating a scanning circuit output (OT).
Here, the clocked inverter (INV1) in an odd-numbered-stage unit circuit inverts the input signal when a clock (CLK) assumes a High level (inverting clock (CLKB) being at a Low level), and the clocked inverter (INV3) in the unit circuit in the same stage inverts the input signal when the clock (CLK) assumes a Low level ((inverting clock (CLKB) being at a High level).
On the other hand, in the clocked inverter (INV1, INV3) in an even-numbered-stage unit circuit, the relationship with the clock which inverts the input signal is opposite to the relationship with the clock in the odd-numbered-stage unit circuit.
Here, JP-A-2002-215118 discloses the nMOS single-channel shift register circuit which is constituted of the nMOS single-channel transistor.
FIG. 15 is a circuit diagram showing an actual circuit constitution of the unit circuit shown in FIG. 14. An input signal IN(S) in FIG. 15 corresponds to an input signal (IN) in FIG. 14, while a scanning circuit output OT(S) in FIG. 15 corresponds to a scanning circuit output (OT) in FIG. 14.
As shown in FIG. 13, in the conventional scanning circuit, the level shift circuit 11 is provided for every line separately from the shift register circuit 10. Further, FIG. 16 is a circuit diagram showing the circuit constitution of one example of the level shift circuit 11 shown in FIG. 13.
A level conversion circuit shown in FIG. 16 is a so-called cross-type level conversion circuit, wherein a signal (IN(L)) which is a low-voltage signal and an inverted signal (INB(L)) thereof are inputted to the level conversion circuit and signals (OT(L), OTB(L)) which are high-voltage signals are outputted from the level conversion circuit. Here, a signal IN(L) in FIG. 16 corresponds to the scanning circuit output (OT(S)) in FIG. 15.
Recently, the development of high definition is in progress in an active matrix liquid crystal display device which is used in a digital still camera, a mobile phone or the like.
Along with the development of high definition, in a conventional scanning circuit, as shown in FIG. 15 and FIG. 16, the number of transistor elements is increased (the unit circuit of the shift register circuit 10 having 16 transistor elements and the unit circuit of the level shift circuit 11 having 6 transistor elements) in the conventional scanning circuit thus giving rise to a drawback that the achievement of high definition is difficult.
Further, p-type MOS transistors (PM1, PM2) and n-type MOS transistors (NM1, NM2) shown in FIG. 15 are configured such that a gate is directly connected to a clock bus through which a clock (CLK) and an inverted clock (CLKB) are transmitted and hence, a load of the clock bus is increased thus giving rise to a drawback that the power consumption is increased.
Further, the p-type MOS transistors (PM1, PM2) and the n-type MOS transistors (NM1, NM2) shown in FIG. 15 are operated for every clock and hence, the transistor is remarkably deteriorated thus giving rise to a drawback with respect to the reliability thereof in a high speed operation.
On the other hand, recently, to cope with a demand for low power consumption and hence, it is necessary to lower amplitude of the clock which consumes the power most. However, here exists a drawback that the conventional circuit constitution cannot lower the amplitude of the clock.
Further, for example, although the nMOS single-channel shift register circuit which is described in the previously-mentioned JP-A-2002-215118 realizes the low input capacitance and the high reliability, the shift register circuit has a drawback that the reduction of voltage and the high-speed driving are difficult.
The present invention has been made to overcome the above-mentioned drawbacks of the related art and it is an object of the present invention to provide a display device which includes a drive circuit having a CMOS shift register circuit which is constituted of a simple CMOS circuit.
The above-mentioned and other objects of the present invention and novel features of the present invention will become apparent from the description of this specification and attached drawings.